Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller known as a “north bridge,” which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a peripheral connect interface (“PCI”) bus.
Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data or latency can significantly slow the operating speed of a computer system using such SDRAM devices.
Another situation which increases latency in a conventional system memory is where a write command is immediately followed by a read command. When the controller issues a write command, the controller must wait until the write data is no longer present on or has “cleared” the data bus. This waiting by the controller increases the latency of the system memory because the read command cannot be applied to a required memory device until later in time. No data is being transferred on the data bus for a longer time after the write data has cleared the bus due to the latency of the memory devices, which lowers the bandwidth of the system memory. As frequencies increase, conventional system topologies can not meet timing requirements due to physical and electrical limitations. Thus memory hubs, a point to point solution are implemented.
One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory controller is coupled over a high speed data link to several memory modules. Typically, the memory modules are coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Thus, the memory controller is coupled to a first memory module over a first high speed data link, with the first memory module connected to a second memory module through a second high speed data link, and the second memory module coupled to a third memory module through a third high speed data link, and so on in a daisy chain fashion.
Each memory module includes a memory hub that is coupled to the corresponding high speed data links and a number of memory devices on the module, with the memory hubs efficiently routing memory requests and responses between the controller and the memory devices over the high speed data links. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor. Moreover, this architecture also provides for easy expansion of the system memory without concern for degradation in signal quality as more memory modules are added, such as occurs in conventional multi drop bus architectures.
Although computer systems using memory hubs may provide superior performance, they nevertheless may often fail to operate at optimum speeds for a variety of reasons. For example, even though memory hubs can provide computer systems with a greater memory bandwidth, they still suffer from latency problems of the type described above. One problem arises as write commands propagate from one memory hub to another. While a write command is propagating downstream, the controller must wait before issuing a subsequent read command to ensure no collision of data. Thus, although a given write command may be directed to the first hub downstream from the controller, for example, the controller must wait until it is sure the data has propagated to the last hub before issuing a subsequent read command to the last hub. This waiting by the controller delays the issuance of the read command and thereby increases the latency of the memory system.
There is a need for a system and method for reducing the latency of a system memory having a memory hub architecture.